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Chapter 4: System Overview 31

Control Subsystem

The Edge Control Subsystem is shown in the figure below.

Figure 4.6 Control Subsystem Block Diagram

The core control subsystem contains the processor, the system bus, the system memory resources of FLASH and

RAM, the interrupt logic, system timers, a DMA engine, and a floating point unit. Support for the ultrasound sub-

system consists of a scanhead interface, scanhead mux control.

Communication interfaces consists of an Ethernet interface, USB port, two general purpose serial bus interfaces,

and the IIC bus. The EDGE control architecture is an open architecture. It supports functionality extension through

the incorporation of the PCI bridge to the PCI bus. Functionality may be added by adding to the PCI Bus.

PROCESSOR

DATA

ADDRESS

CONTROL

FLOATING

POINT

DMA

SYSTEM BUS

SYSTEM

FLASH

SYSTEM

RAM

INTERRUPTS

VIDEO

SYSTEM

TIMERS

ETHERNET

DUAL UART,

USB

cache

FAST

ETHERNET

MASS

STORAGE

IIC BUS

DATA

CONTROL

JTAG

INFRASTRUCTURE

SYSPWR,

SYSCLKS,

SYSRST

PCI BUS

PCI BRIDGE

ULTRASOUND

DATA PATH

SCANHEAD

SH BUS

ECG

U/I, DEBUG

USB

IIC

CONTROLLER

GPIO

CONTROL

SH MUX

CONTROL

AUDIO

EXPANSION

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